The present invention relates to a semiconductor device having a dynamic circuit and a static circuit and having means for matching the operation timing of the circuits.
Recently, semiconductor devices such as static metal oxide semiconductor (MOS) memory devices incorporate dynamic circuits for the reduction of power dissipation (See: F. Baba et al "A 35 ns Static Column DRAM", 1983 IEEE International Solid-state Circuits Conference, Digest of Technical Papers, Article No. WPM6.5, pp 64-65, Feb. 1983).
A static circuit uses mainly depletion-type load transistors, so the operation of the static circuit is carried out without clock signals. Contrary to this, a dynamic circuit is controlled by clock signals, that is, the active mode and reset mode of the dynamic circuit are controlled by clock signals.
In addition, the dependency of the operation of the two types of circuit differs. That is, in a dynamic circuit, the higher the operating speed, the higher the power supply voltage. Contrary to this, in a static circuit, the operating speed is increased only slightly even when the power supply voltage becomes high. Therefore, when the operation timing of the dynamic circuit is shifted due to the fluctuation of the power supply voltage, the operation of the dynamic circuit cannot be matched with that of the static circuit, so that the subsequent downstream circuit cannot be normally operated.